PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 311

• Manufacturer Part Number: PEB2256H-V12
• Description: IC INTERFACE LINE 3.3V 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2256H-V12

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2256H-V12; PEB2256H-V12IN

RFS
T8MS
RMB
CASC
Data Sheet
The complete message length can be determined reading the RBCH,
RBCL registers, the number of bytes currently stored in RFIFO is
given by RBC(4:0). Additional information is available in the RSIS
register.
Receive Frame Start - HDLC Channel 1
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an RFS
interrupt, the contents of
• RAL1
• RSIS bits 3 to 1
are valid and can be read by the CPU.
Receive Time Out 8 ms
Only active if multiframing is enabled.
The framer has found the double framing (basic framing)
FRS0.LFA = 0 and is searching for the multiframing. This interrupt is
set to indicate that no multiframing was found within a time window of
8 ms. In multiframe synchronous state this interrupt is not generated.
Refer also to floating multiframe alignment window.
Receive Multiframe Begin
This bit is set with the beginning of a received CRC multiframe related
to the internal receive line timing.
In CRC multiframe format FMR2.RFS1 = 1 or in doubleframe format
FMR2.RFS(1:0) = 01
FMR2.RFS(1:0) = 00 this interrupt is generated every doubleframe
(512 bits).
Received CAS Information Changed
This bit is set with the updating of a received CAS multiframe
information in the registers RS(16:1). If the last received CAS
information is different to the previous received one, this interrupt is
generated after update has been completed. This interrupt only
occurs only in TS0 and TS16 synchronous state. The registers
RS(16:1) should be read within the next 2 ms otherwise the contents
is lost.
311
this
interrupt
occurs
every
FALC56 V1.2
E1 Registers
PEB 2256
2
2002-08-27
ms.
If