PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 46
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PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2256H-V12
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Table 4
Pin
No.
60
61
62
63
Data Sheet
Ball
No.
B8
A9
A8
B7
Pin Definitions - System Interface (cont’d)
Symbol
XPA
XPB
XPC
XPD
Input (I)
Output (O)
Supply (S)
I + PU
O
O
Function
Transmit Clock (TCLK)
PC(1:4).XPC(3:0) = 0011
A 2.048/8.192-MHz (E1) or 1.544/6.176-MHz
(T1/J1) clock has to be sourced by the system
if the internally generated transmit clock
(generated by DCO-X) shall not be used.
Optionally this input is used as a
synchronization clock for the DCO-X circuitry
with a frequency of 2.048 (E1) or 1.544 MHz
(T1/J1).
Transmit Multiframe Begin (XMFB)
PC(1:4).XPC(3:0) = 0100
XMFB marks the beginning of every
transmitted multiframe on XDI. The signal is
active high for one 2.048 (E1) or 1.544 MHz
(T1/J1) period.
Transmit Signaling Marker (XSIGM)
PC(1:4).XPC(3:0) = 0101
E1: Marks the transmit time slots on XDI of
every frame which are defined by register
TTR(1:4).
T1/J1: Marks the transmit time slots on XDI of
every frame which are defined by register
TTR(1:4) (if not CAS-BR is used).
When using the CAS-BR signaling scheme the
robbed bit of each channel in every sixth frame
is marked.
46
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27
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