ATmega168P Atmel Corporation, ATmega168P Datasheet - Page 175

no-image

ATmega168P

Manufacturer Part Number
ATmega168P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168P

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATmega168PA-15AZ
Manufacturer:
VAC
Quantity:
120
Price:
Company:
CHD Technology Co.,Limited CHD Technology Co.,Limited
Part Number:
ATmega168PA-AU
Manufacturer:
MICROCHIP
Quantity:
250
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATmega168PA-MU
Manufacturer:
ATMEL
Quantity:
4 000
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATmega168PA-PU
Manufacturer:
TI
Quantity:
1 240
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ATmega168PB-AU
Manufacturer:
ATMEL
Quantity:
1 000
Price:
20.3
8025M–AVR–6/11
Clock Generation
Figure 20-1. USART Block Diagram
Note:
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
1. Refer to
Figure 1-1 on page 2
UCSRnA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn(Transmit)
UBRRn [H:L]
(1)
and
Table 14-9 on page 86
UCSRnB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
ATmega48P/88P/168P
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
for USART0 pin placement.
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
RX
TX
Receiver
UCSRnC
XCKn
TxDn
RxDn
175

Related parts for ATmega168P