ATmega168P Atmel Corporation, ATmega168P Datasheet - Page 68

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ATmega168P

Manufacturer Part Number
ATmega168P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168P

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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13. External Interrupts
13.1
68
Pin Change Interrupt Timing
ATmega48P/88P/168P
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT[23:0] pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT[23:0] pins
are configured as outputs. This feature provides a way of generating a software interrupt. The
pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin toggles. The pin change
interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles. The pin change interrupt PCI0
will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-
ters control which pins contribute to the pin change interrupts. Pin change interrupts on
PCINT[23:0] are detected asynchronously. This implies that these interrupts can be used for
waking the part also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Register A – EICRA.
When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-
rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge
interrupts on INT0 or INT1 requires the presence of an I/O clock, described in
and their Distribution” on page
nously. This implies that this interrupt can be used for waking the part also from sleep modes
other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
An example of timing of a pin change interrupt is shown in
Figure 13-1. Timing of pin change interrupts
”System Clock and Clock Options” on page
pcint_setflag
pcint_in_(0)
PCINT(0)
pcint_syn
pin_sync
pin_lat
PCINT(0)
PCIF
clk
clk
LE
pin_lat
27. Low level interrupt on INT0 and INT1 is detected asynchro-
D
Q
pin_sync
PCINT(0) in PCMSK(x)
27.
pcint_in_(0)
0
x
clk
Figure
pcint_syn
13-1.
pcint_setflag
PCIF
”Clock Systems
8025M–AVR–6/11

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