ATmega168P Atmel Corporation, ATmega168P Datasheet - Page 239

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ATmega168P

Manufacturer Part Number
ATmega168P
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega168P

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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22.9
22.9.1
22.9.2
8025M–AVR–6/11
Register Description
TWBR – TWI Bit Rate Register
TWCR – TWI Control Register
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
This is summarized in
Figure 22-21. Possible Status Codes Caused by Arbitration
• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 219
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
Bit
(0xB8)
Read/Write
Initial Value
Bit
(0xBC)
Read/Write
Initial Value
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
START
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
Address / General Call
Figure
Direction
received
Own
TWBR6
TWEA
R/W
R/W
Yes
Arbitration lost in SLA
6
0
6
0
SLA
22-21. Possible status values are given in circles.
Write
Read
TWBR5
TWSTA
R/W
R/W
No
5
0
5
0
TWSTO
TWBR4
R/W
R/W
4
0
4
0
68/78
38
B0
Arbitration lost in Data
TWBR3
TWWC
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
R/W
R
3
0
3
0
ATmega48P/88P/168P
Data
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
0
”Bit Rate Generator
TWBR0
TWIE
R/W
R/W
0
0
0
0
STOP
TWBR
TWCR
239

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