ATmega168P Atmel Corporation, ATmega168P Datasheet - Page 20
Manufacturer Part Number
Specifications of ATmega168P
Max. Operating Frequency
# Of Touch Channels
Hardware Qtouch Acquisition
Max I/o Pins
Adc Resolution (bits)
Adc Speed (ksps)
Resistive Touch Screen
Self Program Memory
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Mpu / Mmu
no / no
Output Compare Channels
Input Capture Channels
Calibrated Rc Oscillator
EEPROM Data Memory
Data Memory Access Times
EEPROM Read/Write Access
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
The ATmega48P/88P/168P contains 256/512/512 bytes of data EEPROM memory. It is orga-
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and
the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
”Memory Programming” on page 291
in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
”Preventing EEPROM Corruption” on page 21
is likely to rise or fall slowly on power-up/down. This causes the device for some
On-chip Data SRAM Access Cycles
Memory Access Instruction
contains a detailed description on EEPROM Programming
for details on how to avoid problems in these
cycles as described in
8-2. A self-timing function, however,