ATmega168P Atmel Corporation, ATmega168P Datasheet - Page 94
Manufacturer Part Number
Specifications of ATmega168P
Max. Operating Frequency
# Of Touch Channels
Hardware Qtouch Acquisition
Max I/o Pins
Adc Resolution (bits)
Adc Speed (ksps)
Resistive Touch Screen
Self Program Memory
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Mpu / Mmu
no / no
Output Compare Channels
Input Capture Channels
Calibrated Rc Oscillator
Timer/Counter Clock Sources
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
shows a block diagram of the counter and its surroundings.
See Section “16.7.3” on page 121.
”Timer/Counter0 and Timer/Counter1 Prescalers” on page
is present or not. A CPU write overrides (has priority over) all counter clear or
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
can be generated from an external or internal clock source,
for details. The compare match event will also set the
( From Prescaler )
in the following.