ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 100

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.10 Timer/Counter0 Prescaler
10.11 Register Description
10.11.1
100
ATtiny87/ATtiny167
TCCR0A – Timer/Counter0 Control Register A
Figure 10-12. Prescaler for Timer/Counter0
The clock source for Timer/Counter0 is named clk
main system I/O clock clk
nously clocked from the XTAL oscillator or XTAL1 pin. This enables use of Timer/Counter0 as
a Real Time Counter (RTC).
A crystal can then be connected between the XTAL1 and XTAL2 pins to serve as an indepen-
dent clock source for Timer/Counter0.
A external clock can also be used using XTAL1 as input. Setting AS0 and EXCLK enables this
configuration.
For Timer/Counter0, the possible prescaled selections are: clk
clk
selected. Setting the PSR0 bit in GTCCR resets the prescaler. This allows the user to operate
with a predictable prescaler.
• Bits 7:6 – COM0A[1:0]: Compare Match Output Mode A
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0]
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con-
nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A
pin must be set in order to enable the output driver.
Bit
0x25 (0x45)
Read/Write
Initial Value
T
0
XTAL2
XTAL1
S
/128, clk
COM0A1
T
R/W
Oscillator
0
7
0
S
/256, and clk
EXCLK
PSRn
CSn0
CSn1
CSn2
COM0A0
R/W
6
0
clk
IO
0
1
I/O
. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchro-
ASn
T
0
R
5
–
0
S
0
1
/1024. Additionally, clk
clk
TnS
R
4
–
0
Clear
T
0
TIMER/COUNTERn CLOCK SOURCE
R
3
–
0
S
. clk
0
T
0
T
10-BIT T/C PRESCALER
S
0
R
2
–
0
S
is by default connected to the
clk
as well as 0 (stop) may be
T
Tn
0
S
WGM01
/8, clk
R/W
1
0
T
0
S
WGM00
/32, clk
R/W
0
0
8265B–AVR–09/10
T
TCCR0A
0
S
/64,