ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 95

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.7.4
8265B–AVR–09/10
Phase Correct PWM Mode
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the
interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
Setting the COM0A[1:0] bits to two will produce a non-inverted PWM and an inverted PWM
output can be generated by setting the COM0A[1:0] to three (See
The actual OC0A value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by setting (or clearing) the OC0A Register at
the compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register
at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will
result in a constantly high or low output (depending on the polarity of the output set by the
COM0A[1:0] bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC0A to toggle its logical level on each compare match (COM0A[1:0] = 1). The wave-
form generated will have a maximum frequency of f
This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
Output Compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM0[1:0] = 1) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOT-
TOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the
compare match between TCNT0 and OCR0A while upcounting, and set on the compare
match while downcounting. In inverting Output Compare mode, the operation is inverted. The
dual-slope operation has lower maximum operation frequency than single slope operation.
However, due to the symmetric feature of the dual-slope PWM modes, these modes are pre-
ferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the coun-
ter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for
one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
ure
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent compare matches between
OCR0A and TCNT0.
10-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the
f
OCnxPWM
=
oc
----------------- -
N 256
f
0
clk_I/O
⋅
A
= f
clk_I/O
/2 when OCR0A is set to zero.
Table 10-2 on page
101).
Fig-
95