ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 209

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11.4
17.11.5
8265B–AVR–09/10
ADCSRB – ADC Control and Status Register B
DIDR0 – Digital Input Disable Register 0
• Bit 7 – BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be
selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided
conversions are supported and the voltage on the positive input must always be larger than
the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In
the bipolar mode two-sided conversions are supported and the result is represented in the
two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the
resolution is 9 bits + 1 sign bit.
• Bit 3 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to
zero when ADCSRB register is written.
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA register is written to one, the value of these bits selects which source
will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect.
A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that
switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA register is set, this will start a conver-
sion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the
ADC Interrupt Flag is set.
Table 17-7.
Bit
(0x7B)
Read/Write
Initial Value
Bit
(0x7E)
Read/Write
Initial Value
ADTS2
0
0
0
0
1
1
1
1
ADC7D /
ADC Auto Trigger Source Selections
AIN1D
R/W
R/W
BIN
7
0
7
0
ADTS1
ADC6D /
0
0
1
1
0
0
1
1
AIN0D
ACME
R/W
R/W
6
0
6
0
ADC5D
ACIR1
R/W
R/W
0
5
5
0
ADTS0
0
1
0
1
0
1
0
1
ADC4D
ACIR0
R/W
R/W
4
0
4
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter1 Compare Match A
Timer/Counter1 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Capture Event
Watchdog Interrupt Request
ADC3D
R/W
R
3
0
3
–
0
ADC2D
ADTS2
R/W
R/W
2
0
2
0
ADC1D
ADTS1
R/W
R/W
1
0
1
0
ADC0D
ADTS0
R/W
R/W
0
0
0
0
ADCSRB
DIDR0
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