ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 116

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.5
116
Counter Unit
ATtiny87/ATtiny167
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter
unit.
Figure 12-2. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H)
containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower
eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU
does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary regis-
ter (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is
read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the
8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1
Register when the counter is counting that will give unpredictable results. The special cases
are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
clock source, selected by the Clock Select bits (CS1[2:0]). When no clock source is selected
(CS1[2:0] = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,
independent of whether clk
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM1[3:0]) located in the Timer/Counter Control Registers A and B (TCCR1A and
TCCR1B). There are close connections between how the counter behaves (counts) and how
waveforms are generated on the Output Compare outputs OC1A/B. For more details about
advanced counting sequences and waveform generation, see
122.
Figure 12-2
Count
Direction
Clear
clk
TOP
BOTTOM
TCNTnH (8-bit)
T
TEMP (8-bit)
1
TCNTn (16-bit Counter)
DATA BUS
shows a block diagram of the counter and its surroundings.
TCNTnL (8-bit)
(8-bit)
T
1 is present or not. A CPU write overrides (has priority over) all
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock.
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
T
1). The clk
Direction
Count
Clear
TOP
T
1 can be generated from an external or internal
Control Logic
BOTTOM
TOVn
(Int.Req.)
clk
Tn
“Modes of Operation” on page
Clock Select
( From Prescaler )
Detector
Edge
8265B–AVR–09/10
Tn