ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 17

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.2.1
3.3
8265B–AVR–09/10
EEPROM Data Memory
Data Memory Access Times
Figure 3-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 3-3.
The ATtiny87/167 contains EEPROM memory (see “E2 size” in
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-
ters, the EEPROM Data Register and the EEPROM Control Register.
Section 21. “Memory Programming” on page 225
programming in SPI or Parallel Programming mode.
Address
clk
Data
Data
Data Memory Map
On-chip Data SRAM Access Cycles
WR
CPU
RD
Compute Address
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
Data Memory
(ISRAM size)
32 Registers
T1
Memory Access Instruction
Address valid
0x0000 - 0x001F
ISRAM start
ISRAM end
0x0020 - 0x005F
0x0060 - 0x00FF
T2
contains a detailed description on EEPROM
CPU
cycles as described in
Next Instruction
Table 3-1 on page
T3
Figure
3-3.
15). It is
17