ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 46

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.8.6
5.8.7
5.8.8
5.9
5.9.1
46
Register Description
ATtiny87/ATtiny167
Watchdog Timer
Port Pins
On-chip Debug System
SMCR – Sleep Mode Control Register
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume
power. In the deeper sleep modes, this will contribute significantly to the total current con-
sumption. Refer to
the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
72
left floating or have an analog signal level close to V
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
Section 17.11.5 “DIDR0 – Digital Input Disable Register 0” on page 209
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode,
the main clock source is enabled and hence always consumes power. In the deeper sleep
modes, this will contribute significantly to the total current consumption.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bits 2:1 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between the four available sleep modes as shown in
Bit
0x33 (0x53)
Read/Write
Initial Value
for details on which pins are enabled. If the input buffer is enabled and the input signal is
CC
I/O
R
7
–
0
Section 17.11.6 “DIDR1 – Digital Input Disable Register 1” on page 210
/2 on an input pin can cause significant current even in active mode. Digital
) and the ADC clock (clk
Section 6.3 “Watchdog Timer” on page 53
R
6
–
0
Section 9.2.6 “Digital Input Enable and Sleep Modes” on page
R
5
–
0
ADC
R
4
–
0
) are stopped, the input buffers of the device will
R
3
–
0
CC
/2, the input buffer will use excessive
SM1
R/W
2
0
for details on how to configure
SM0
R/W
1
0
Table
for details.
5-2.
R/W
SE
0
0
8265B–AVR–09/10
SMCR
and