ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 63

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.3
8.3.1
8.3.2
8265B–AVR–09/10
Register Description
EICRA – External Interrupt Control Register A
EIMSK – External Interrupt Mask Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bits 3:2 – ISC1[1:0]: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 8-1.
• Bits 7:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
Bit
(0x69)
Read/Write
Initial Value
Bit
0x1D (0x3D)
Read/Write
Initial Value
ISCn1
0
0
1
1
Interrupt Sense Control
ISCn0
R
7
–
0
R
7
–
0
0
1
0
1
Table
Table
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge of INTn generates an interrupt request.
The rising edge of INTn generates an interrupt request.
R
6
–
0
R
6
–
0
8-1. The value on the INT1 pin is sampled before detecting
8-1. The value on the INT0 pin is sampled before detecting
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
ISC11
R/W
3
0
R
3
–
0
ISC10
R/W
2
0
R
2
–
0
ISC01
R/W
INT1
R/W
1
0
1
0
ISC00
R/W
INT0
R/W
0
0
0
0
EICRA
EIMSK
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