ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 7
ATtiny167
Manufacturer Part Number
ATtiny167
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny167
Flash (kbytes)
16 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ATMEL
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670
Company:
Part Number:
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Manufacturer:
ATMEL
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480
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Manufacturer:
ATMEL/爱特梅尔
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Part Number:
ATtiny167-A15XD
Manufacturer:
BOSCH
Quantity:
40 000
Part Number:
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Quantity:
20 000
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2. AVR CPU Core
2.1
8265B–AVR–09/10
Overview
This section discusses the AVR core architecture in general. The main function of the CPU
core is to ensure correct program execution. The CPU must therefore be able to access mem-
ories, perform calculations, control peripherals, and handle interrupts.
Figure 2-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the Program memory. This concept enables instructions to be
executed in every clock cycle. The Program memory is In-System Reprogrammable Flash
memory. The fast-access Register File contains 32 x 8-bit general purpose working registers
with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File, the
operation is executed, and the result is stored back in the Register File – in one clock cycle.
Control Lines
Instruction
Instruction
Program
Memory
Register
Decoder
Flash
Block Diagram of the AVR Architecture
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
I/O Module1
Comparator
I/O Module 2
I/O Module n
Watchdog
Interrupt
Timer
A.D.C.
Analog
Unit
7
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