ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 99

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8265B–AVR–09/10
• When the asynchronous operation is selected, the oscillator for Timer/Counter0 is always
• Description of wake up from Power-save mode when the timer is clocked asynchronously:
• Reading of the TCNT0 Register shortly after wake-up from Power-save may give an
• During asynchronous operation, the synchronization of the interrupt flags for the
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less
than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the
user is in doubt whether the time before re-entering Power-save mode is sufficient, the
following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
running, except in Power-down mode. After a Power-up Reset or wake-up from
Power-down mode, the user should be aware of the fact that this oscillator might take as
long as one second to stabilize. The user is advised to wait for at least one second before
using Timer/Counter0 after power-up or wake-up from Power-down mode. The contents of
all Timer/Counter0 Registers must be considered lost after a wake-up from Power-down
mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use
or a clock signal is applied to the XTAL1 pin.
When the interrupt condition is met, the wake up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor
can read the counter value. After wake-up, the MCU is halted for four cycles, it executes
the interrupt routine, and resumes execution from the instruction following SLEEP.
incorrect result. Since TCNT0 is clocked on the asynchronous clock, reading TCNT0 must
be done through a register synchronized to the internal I/O clock domain (CPU main clock).
Synchronization takes place for every rising XTAL1 edge. When waking up from
Power-save mode, and the I/O clock (clk
previous value (before entering sleep) until the next rising XTAL1 edge. The phase of the
XTAL1 clock after waking up from Power-save mode is essentially unpredictable, as it
depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as
follows:
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the interrupt flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
a. Write a value to TCCR0A, TCNT0, or OCR0A.
b. Wait until the corresponding Update Busy flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
a. Write any value to either of the registers OCR0A or TCCR0A.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT0.
I/O
) again becomes active, TCNT0 will read as the
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