ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 101

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ATtiny167

Manufacturer Part Number
ATtiny167
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny167

Flash (kbytes)
16 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8265B–AVR–09/10
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the
WGM0[1:0] bit setting.
WGM0[1:0] bits are set to a normal or CTC mode (non-PWM).
Table 10-1.
Table 10-2
PWM mode.
Table 10-2.
Note:
Table 10-3
correct PWM mode.
Table 10-3.
Note:
• Bits 5:2 – Res: Reserved Bits
These bits are reserved in the ATtiny87/167 and will always read as zero.
COM0A1
COM0A1
COM0A1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
94
pare Match is ignored, but the set or clear is done at TOP. See
on page 95
shows the COM0[1:0] bit functionality when the WGM0[1:0] bits are set to phase
shows the COM0A[1:0] bit functionality when the WGM0[1:0] bits are set to fast
for more details.
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0A0
COM0A0
COM0A0
0
1
0
1
0
1
0
1
0
1
0
1
for more details.
Table 10-1
Description
Normal port operation, OC0A disconnected.
Clear OC0A on Compare Match.
Set OC0A at BOTTOM (non-inverting mode).
Set OC0A on Compare Match.
Clear OC0A at BOTTOM (inverting mode).
Description
Normal port operation, OC0A disconnected.
Clear OC0A on Compare Match when up-counting.
Set OC0A on Compare Match when down-counting.
Set OC0A on Compare Match when up-counting.
Clear OC0A on Compare Match when down-counting.
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match.
Clear OC0A on Compare Match.
Set OC0A on Compare Match.
shows the COM0A[1:0] bit functionality when the
(1)
(1)
“Phase Correct PWM Mode”
“Fast PWM Mode” on page
101

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