ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 214

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.2.3
214
ATtiny87/ATtiny167
DIDR0 – Digital Input Disable Register 0
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog
Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to
the input capture front-end logic, making the comparator utilize the noise canceler and edge
select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no con-
nection between the Analog Comparator and the input capture function exists. To make the
comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Inter-
rupt Mask Register (TIMSK1) must be set.
• Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in
Table 18-3.
Note:
• Bits 7:6 – AIN1D, AIN0D: AIN1 and AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding Analog Com-
pare pin is disabled. The corresponding PIN register bit will always read as zero when this bit
is set. When an analog signal is applied to the AIN0/1 pin and the digital input from this pin is
not needed, this bit should be written logic one to reduce power consumption in the digital
input buffer.
Bit
(0x7E)
Read/Write
Initial Value
ACIS1
0
0
1
1
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when
the bits are changed.
ADC7D /
ACIS1 / ACIS0 Settings
AIN1D
R/W
7
0
ACIS0
0
1
0
1
ADC6D /
AIN0D
R/W
6
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
ADC5D
R/W
5
0
Table
ADC4D
18-3.
R/W
4
0
ADC3D
R/W
3
0
ADC2D
R/W
2
0
ADC1D
R/W
1
0
ADC0D
R/W
0
0
8265B–AVR–09/10
DIDR0