ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 70

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.5
70
ATtiny87/ATtiny167
Reading the Pin Value
Table 9-1
Table 9-1.
Note:
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
constitute a synchronizer. This is needed to avoid metastability if the physical pin changes
value near the edge of the internal clock, but it also introduces a delay.
timing diagram of the synchronization when reading an externally applied pin value. The max-
imum and minimum propagation delays are denoted t
Figure 9-4.
Consider the clock period starting shortly after the first falling edge of the system clock. The
latch is closed when the clock is low, and goes transparent when the clock is high, as indi-
cated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the
system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock
edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin
will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
DDxn
0
0
0
1
1
1. Or port-wise PUDx bit in PORTCR register.
Figure
summarizes the control signals for the pin value.
INSTRUCTIONS
PORTxn
SYSTEM CLK
SYNC LATCH
0
1
1
0
1
Port Pin Configurations
Synchronization when Reading an Externally Applied Pin value
9-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
r17
(in MCUCR)
PUD
X
X
X
0
1
Figure
(1)
XXX
Output
Output
Input
Input
Input
9-2, the PINxn Register bit and the preceding latch
I/O
t
pd, max
0x00
Pull-up
XXX
Yes
No
No
No
No
t
pd, min
pd,max
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
and t
in r17, PINx
pd,min
respectively.
Figure 9-4
0xFF
8265B–AVR–09/10
shows a