ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 62

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. External Interrupts
8.1
8.2
62
Overview
Pin Change Interrupt Timing
ATtiny87/ATtiny167
The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT[15:0] pins.
Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT[15:0] pins
are configured as outputs. This feature provides a way of generating a software interrupt.
The pin change interrupt PCINT1 will trigger if any enabled PCINT[15:8] pin toggles. The pin
change interrupt PCINT0 will trigger if any enabled PCINT[7:0] pin toggles. The PCMSK1 and
PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change
interrupts on PCINT[15:0] are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than Idle mode.
The INT0 or INT1 interrupt can be triggered by a falling or rising edge or a low level. This is set
up as indicated in the specification for the External Interrupt Control Register A – EICRA.
When the INT0 or INT1 interrupt is enabled and is configured as level triggered, the interrupt
will trigger as long as the pin is held low. The recognition of falling or rising edge interrupts on
INT0 or INT1 requires the presence of an I/O clock, described in
tribution” on page
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle
mode.
Note that if a level triggered interrupt is used for wake-up from Power-down or Power-save,
the required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still
wake up, but no interrupt will be generated. The start-up time is defined by the SUT and
CKSEL Fuses as described in
An example of timing of a pin change interrupt is shown in
Figure 8-1.
PCINT[i]
pin
clk
pcint_set/flag
PCINT[i] pin
pcint_in[i]
pcint_syn
pin_sync
Timing of pin change interrupts
pin_lat
D
LE
PCIF
clk
Q
24. Low level interrupts and the edge interrupt on INT0 or INT1 are detected
n
pin_lat
D
Q
pin_sync
“Clock Systems and their Distribution” on page
(of PCMSK
PCINT[i] bit
n
)
pcint_in[i]
0
7
clk
Figure
D
Q
“Clock Systems and their Dis-
pcint_sync
8-1.
D
Q
pcint_set/flag
D
24.
Q
8265B–AVR–09/10
(interrupt flag)
PCIF
n