ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 69

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.2.2
9.2.3
9.2.4
8265B–AVR–09/10
Toggling the Pin
Break-Before-Make Switching
Switching Between Input and Output
YSTEM CLOCK
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port.
In the Break-Before-Make mode when switching the DDRxn bit from input to output an imme-
diate tri-state period lasting one system clock cycle is introduced as indicated in
For example, if the system clock is 4 MHz and the DDRxn is written to make an output, the
immediate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the
port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is
two system clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the
port-wise BBMx enable bits. For further information about the BBMx bits, see
Control Register” on page
immediate tri-state period introduced.
Figure 9-3.
NSTRUCTIONS
W h e n s w i t c h i n g b e t w e e n t r i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) a n d o u t p u t h i g h
( { D D x n , P O R T x n } = 1 , 1 ) , a n i n t e r m e d i a t e s t a t e w i t h e i t h e r p u l l - u p e n a b l e d
{DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the
pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the
MCUCR Register or the PUDx bit in PORTCR Register can be set to disable all pull-ups in the
port.
Switching between input with pull-up and output low generates the same problem. The user
m u s t u s e e it h e r t h e t r i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) o r t h e o u t p u t h i g h s t a t e
({DDxn, PORTxn} = 1, 1) as an intermediate step.
PORTx
DDRx
R 16
R 17
Px0
Px1
Break Before Make, switching between input and output
out DDRx, r16
0x01
75. When switching the DDRxn bit from output to input there is no
tri-state
immediate tri-state cycle
0x02
0x01
0x55
0x02
nop
tri-state
out DDRx, r17
immediate tri-state cycle
“PORTCR – Port
0x01
tri-state
Figure
9-3.
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