ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 185

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ATtiny167

Manufacturer Part Number
ATtiny167
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny167

Flash (kbytes)
16 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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15.6.6
15.6.7
8265B–AVR–09/10
LINBRR – LIN Baud Rate Register
LINDLR – LIN Data Length Register
• Bits 5:0 – LBT[5:0]: LIN Bit Timing
• Bits 15:12 – Res: Reserved Bits
• Bits 11:0 – LDIV[11:0]: Scaling of clk
• Bits 7:4 – LTXDL[3:0]: LIN Transmit Data Length
• Bits 3:0 – LRXDL[3:0]: LIN Receive Data Length
Bit
(0xCD)
(0xCE)
Bit
Read/Write
Initial Value
Bit
(0xCF)
Read/Write
Initial Value
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINBRR is written.
The LDIV value is used to scale the entering clk
UART baud rate.
Gives the number of samples of a bit.
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max).
In UART mode this field is unused.
In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max).
In UART mode this field is unused.
LTXDL3
LDIV7
R/W
R/W
15
7
0
7
0
LTXDL2
sample-time = (1 /
LDIV6
R/W
R/W
14
6
0
6
0
LTXDL1
LDIV5
R/W
R/W
13
5
0
5
0
LTXDL0
i/o
LDIV4
f
R/W
R/W
clk
12
4
0
4
0
Frequency
i/o
) x (LDIV[11:0] + 1)
LRXDL3
LDIV11
LDIV3
R/W
R/W
11
i/o
3
0
3
0
frequency to achieve appropriate LIN or
LRXDL2
LDIV10
LDIV2
R/W
R/W
10
2
0
2
0
LRXDL1
LDIV1
LDIV9
R/W
R/W
1
0
1
9
0
LRXDL0
LDIV0
LDIV8
R/W
R/W
0
0
0
8
0
LINBRRH
LINBRRL
LINDLR
185

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