ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 39

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.5.3
8265B–AVR–09/10
CLKCSR – Clock Control & Status Register
Table 4-10.
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The
CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to
zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits
are written. Rewriting the CLKCCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bit 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability ’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’
command being entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is sta-
ble. The delay from the request and the flag setting is not fixed, it depends on the clock
Bit
(0x62)
Read/Write
Initial Value
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKCCE
Clock Prescaler Select
R/W
7
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R
5
–
0
CLKRDY
R
4
0
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKC3
R/W
3
0
CLKC2
R/W
2
0
Clock Division Factor
CLKC1
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
128
256
16
32
64
1
2
4
8
CLKC0
R/W
0
0
CLKCSR
39