ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 37

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.4
4.4.1
4.4.2
4.5
4.5.1
8265B–AVR–09/10
System Clock Prescaler
Register Description
Features
Switching Time
OSCCAL – Oscillator Calibration Register
The ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither
the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before
the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value
is automatically written to this register during chip reset, giving the Factory calibrated fre-
quency as specified in
register to change the oscillator frequency. The oscillator can be calibrated to frequencies as
specified in
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to
more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in
Bit
(0x66)
Read/Write
Initial Value
Table 22-1 on page
CAL7
R/W
7
CAL6
R/W
Table 22-1 on page
6
245. Calibration outside that range is not guaranteed.
CAL5
R/W
5
Table 4-10 on page
Device Specific Calibration Value
CAL4
R/W
4
245. The application software can write this
CAL3
R/W
3
39.
CAL2
R/W
2
I/O
, clk
CAL1
R/W
ADC
1
, clk
CPU
CAL0
R/W
0
, and clk
OSCCAL
FLASH
37