ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 147

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.2.4
13.2.5
8265B–AVR–09/10
SPSR – SPI Status Register
SPDR – SPI Data Register
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI
is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first read-
ing the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
• Bits 5:1 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work
at f
The SPI interface on the ATtiny87/167 is also used for program memory and EEPROM down-
loading or uploading. See
verification.
• Bits 7:0 – SPD[7:0]: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
Bit
0x2D (0x4D)
Read/Write
Initial Value
Bit
0x2E (0x4E)
Read/Write
Initial Value
clkio
/4 or lower.
SPD7
SPIF
R/W
X
R
7
7
0
WCOL
SPD6
R/W
6
X
R
6
0
Table
“Serial Downloading” on page 238
SPD5
R/W
13-4). This means that the minimum SCK period will be two
5
X
R
0
5
–
SPD4
R/W
X
4
R
4
–
0
SPD3
R/W
X
3
R
3
–
0
SPD2
R/W
X
2
R
2
–
0
for serial programming and
SPD1
R/W
1
X
R
1
–
0
SPD0
SPI2X
R/W
R/W
0
X
0
0
Undefined
SPDR
SPSR
147