ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 43

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.2
5.3
5.4
8265B–AVR–09/10
BOD Disable
Idle Mode
ADC Noise Reduction Mode
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses,
226, the BOD is actively monitoring the power supply voltage during a sleep period. To save
power, it is possible to disable the BOD by software for some of the sleep modes, see
5-1. The sleep mode power consumption will then be at the same level as when BOD is glob-
ally disabled by fuses. If BOD is disabled in software, the BOD function is turned off
immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically
enabled again. This ensures safe operation in case the V
period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately
60 µs to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by BODS bit (BOD Sleep) in the control register MCUCR, see
“MCUCR – MCU Control Register” on page
sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e.
BODS is cleared to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, Analog Comparator, ADC, USI start condition,
Asynchronous Timer/Counter, Watchdog, and the interrupt system to continue operating. This
sleep mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Compara-
tor Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If
the ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the
USI start condition, the asynchronous Timer/Counter and the Watchdog to continue operating
(if enabled). This sleep mode basically halts clk
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements.
If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from
the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a USI start condition interrupt, an asynchronous
Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0
or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
CPU
47.
and clk
FLASH
47. Setting it to one turns off the BOD in relevant
, while allowing the other clocks to run.
I/O
, clk
CPU
CC
level has dropped during the sleep
, and clk
FLASH
Table 21-3 on page
, while allowing the
“MCUCR –
Table
43