ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 31

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.2.7
4.3
4.3.1
8265B–AVR–09/10
Dynamic Clock Switch
Clock Output Buffer
Features
Table 4-9.
Notes:
Note that the System Clock Prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. Refer to
page 37
If not using a crystal oscillator, the device can output the system clock on the CLKO pin. To
enable the output, the CKOUT Fuse or COUT bit of CLKSELR register has to be programmed.
This option is useful when the device clock is needed to drive other circuits on the system.
Note that the clock will not be output during reset and the normal operation of I/O pin will be
overridden when the fuses are programmed. If the System Clock Prescaler is used, it is the
divided system clock that is output.
The ATtiny87/167 provides a powerful dynamic clock switch circuit that allows users to turn on
and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be
enabled or disabled asynchronously. This enables efficient power management schemes to
be implemented easily and quickly. In a safety application, the dynamic clock switch circuit
allows continuous monitoring of the external clock permitting a fallback scheme in case of
clock failure.
The control of the dynamic clock switch circuit must be supervised by software. This operation
is facilitated by the following features:
• Safe commands, to avoid unintentional commands, a special write procedure must be
• Exclusive action, the actions are controlled by a decoding table (commands) written to the
CSUT[1:0]
SUT[1:0]
followed to change the CLKCSR register bits
page
CLKCSR register. This ensures that only one command operation can be launched at any
time. The main actions of the decoding table are:
– ‘Disable Clock Source’,
– ‘Enable Clock Source’,
– ‘Request Clock Availability’,
– ‘Clock Source Switching’,
00
01
10
11
1. Flash Fuse bits.
2. CLKSELR register bits.
3. Additional delay (+ 4ms) available if RSTDISBL fuse is set.
for details.
38.):
(1)
(2)
Start-up Times for the External Clock Selection
Start-up Time from
Power-down/save
6 CK
6 CK
6 CK
Additional Delay from Reset
14CK (+ 4.1 ms
14CK + 4.1 ms
14CK + 65 ms
(V
(See “CLKPR – Clock Prescaler Register” on
CC
Reserved
= 5.0V)
(3)
)
“System Clock Prescaler” on
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
31