ATtiny167 Atmel Corporation, ATtiny167 Datasheet - Page 35

• Manufacturer Part Number: ATtiny167
• Manufacturer: Atmel Corporation

Specifications of ATtiny167

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8265B–AVR–09/10
In the first domain, the user (code) can easily check the validity of the clock(s)
Command” on page
In the second domain, the lack of a clock results in the code not running. Thus, the presence
of the system clock needs to be monitored by hardware.
Using the on-chip watchdog allows this monitoring. Normally, the watchdog reloading is per-
formed only if the code reaches some specific software labels, reaching these labels proves
that the system clock is running. Otherwise the watchdog reset is enabled. This behavior can
be considered as a clock monitoring.
If the standard watchdog functionality is not desired, the ATtiny87/167 watchdog permits the
system clock to be monitored without having to resort to the complexity of a full software
watchdog handler. The solution proposed in the ATtiny87/167 is to automate the watchdog
reloading with only one command, at the beginning of the session.
So, to monitor the system clock, the user will have two options:
The two options are exclusive.
Note:
Figure 4-6.
The ‘Enable Watchdog in Automatic Reload Mode’ command has priority over the standard
watchdog enabling. In this mode, only the reset function of the watchdog is enabled (no more
watchdog interrupt). The WDP[3:0] bits of the WDTCSR register always determine the watch-
dog timer prescaling.
As the watchdog will not be active before executing the ‘Enable Watchdog in Automatic
Reload Mode’ command, it is recommended to activate this command before switching to an
external clock source (See note on
Notes:
1. Using the standard watchdog features (software reload),
2. Or using the automatic reloading (hardware reload).
Warning:
These two options make sense ONLY if the clock source at RESET is an INTERNAL SOURCE.
The fuse settings determine this operation.
1. ONLY the reset (watchdog reset included) disables this function. The Watchdog System
2. ONLY clock frequencies greater than or equal to (4 * WatchDog Clock Frequency) can be
Reset Flag (WDRF bit of MCUSR register) can be used to monitor the reset cause.
monitored.
WDTCSR
Watchdog Timer with Automatic Reloading.
Interrupt
Register:
Reset
WD
WD
33.).
Internal Bus
WatchDog
page
35).
Reload
0
1
Checker
WatchDog Clock
Enable
Automatic
Reloading
Mode
System CLK
(See “COUT
35