r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 110

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
8.3.2
Table 8.3
Notes:
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop conditions
Operation at underflow • When the RIS bit in the RISR register is 0
1. The watchdog timer is initialized by writing 00h and then FFh to the WDTR register. The prescaler is initialized
2. Only write to the WDTR register while the watchdog timer is counting.
3. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 at address 0FFFFh with a flash
When count source protection mode is disabled, the count source for the watchdog timer is the CPU clock or
low-speed on-chip oscillator clock.
Table 8.3 lists the Watchdog Timer Specifications when Count Source Protection Mode is Disabled.
after a reset. This results in discrepancies in the watchdog timer period due to the prescaler.
programmer.
Item
When Count Source Protection Mode is Disabled
Preliminary document
Specifications in this document are tentative and subject to change.
Watchdog Timer Specifications when Count Source Protection Mode is Disabled
CPU clock or low-speed on-chip oscillator clock (1/16) for the watchdog timer
Decrement
n: 2, 16, or 128 (selected by bits WDTC6 and WDTC7 in the WDTC register)
However, when bits WDTC7 and WDTC6 are 11b (count source is low-speed on-chip
oscillator), n is 16.
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Ex.: When the prescaler divides a CPU clock of 20 MHz by 16, and bits WDTUFS1 and
• Reset
• 00h and then FFh are written to the WDTR register
• Underflow
The operation of the watchdog timer after a reset is selected by the WDTON bit
OFS register (address 0FFFFh).
• When the WDTON bit is 1 (watchdog timer stops after reset)
• When the WDTON bit is 0 (watchdog timer automatically starts after reset)
• When the count source is obtained by dividing the CPU clock by 2, 16, or 128, if the MCU
• When the count source is obtained by dividing the low-speed on-chip oscillator by 16,
• When the RIS bit in the RISR register is 1
Prescaler division ratio (n) × Count value of the watchdog timer (m)
enters wait mode or stop mode, count stops.
even if the MCU enters wait mode or stop mode, count does not stop.
The watchdog timer and the prescaler stop after a reset, and only start counting when the
WDTS register is written.
The watchdog timer and the prescaler automatically start counting after a reset.
Watchdog timer interrupt
Watchdog timer reset (refer to 6.3.5 Watchdog Timer Reset .)
WDTUFS0 are 11b (3FFFh), the period is approx. 13.1 ms.
Count source
Specification
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8. Watchdog Timer
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