r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 63

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
4.
4.1
Table 4.1
Note:
SFR
(00002h to 0003Fh)
SFR
(other than 00002h to
0003Fh)
SRAM
Data flash
Program ROM
The number of bus cycles differs depending on the area accessed: ROM, RAM, DTC vector area, DTC control
data, and SFR. For ROM and SFR, the restrictions on the number of access cycles differ depending on the CPU
clock frequency. Thus the number must be set with the control registers (processor mode register (PM1) and flash
control register (FMR2)).
Tables 4.1 lists the Data Bus Widths and Bus Cycles for Accessing Different Areas for the R8C/36T-A Group (with
data flash).
A part of SFR and data flash are connected to the CPU via an 8-bit bus. When these areas are accessed as word (16-
bit) units, they are accessed twice in 8-bit units.
Bus Access
1. The number of cycles to write to the following registers is three wait states.
(1)
Access Target
• SSU/IIC: SISR
• Timer RC: TRCSR
The number of cycles to write to the SITDR register for the SSU/IIC is three wait states.
However, the number of cycles to write to the SITDR register by DTC access is one wait state.
Bus Access
Preliminary document
Specifications in this document are tentative and subject to change.
Data Bus Widths and Bus Cycles for Accessing Different Areas (CPU clock  20 MHz)
Bus Width
(bit)
16
16
16
8
8
Wait Cycles
1 wait state
1 wait state
0 wait state
1 wait state
0 wait state
Number of
Byte Access
2
2
1
2
1
Number of Access Cycles
(even address)
Word Access
4
2
1
4
1
(odd address)
Word Access
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4. Bus Access
4
4
2
4
2