r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 498

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Notes:
21.2.9.2
After Reset
1. Writing 1 to these bits has no effect. Each bit is set to 0 by writing 0 after reading it as 1.
2. Enabled in slave receive mode of I
3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I
4. The NACKF bit is enabled when the ACKE bit in the SIER register is 1 (when the receive acknowledge bit is 1,
5. The RDRF bit is set to 0 when data is read from the SIRDR register. Do not clear this bit by writing 0 when not in
6. Bits TEND and TDRE are set to 0 when data is written to the SITDR register.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 000EAh (SISR_0)
monitors the SDA pin and the data which the I
indicating the bus is occupied by another master.
transfer is halted).
I
Symbol
2
C bus interface mode or when not clearing the RDRF bit after DTC access.
ORER_AL Arbitration lost flag/overrun
CE_ADZ General call address
Bit
Symbol
NACKF
STOP
RDRF
TEND
TDRE
AAS
Preliminary document
Specifications in this document are tentative and subject to change.
I
TDRE
2
C bus Function
b7
0
recognition flag
Slave address recognition
flag
error flag
Stop condition detection
flag
No acknowledge detection
flag
Receive data register full
flag
Transmit end flag
Transmit data empty flag
(1)
(1)
(1, 4)
(1, 5)
TEND
b6
0
(1)
Bit Name
(1, 2)
(1, 6)
RDRF
2
C bus interface mode.
b5
0
(1, 6)
NACKF
2
C bus interface transmits is different, the ORER_AL bit is set to 1
b4
This flag is set to 1 when a general call address is
detected.
This flag is set to 1 when the first frame immediately after
the start condition matches bits SVA0 to SVA6 in the
SIMR2 register in slave receive mode (slave address
detection, general call address detection).
In I
arbitration is lost in master mode. This flag is set to 1
when:
• The internal SDA signal and SDA pin level do not match
• The SDA pin is held high at start condition detection in
In clock synchronous serial mode, this bit indicates that
an overrun error has occurred. This flag is set to 1 when:
• The last bit of the next data is received while the RDRF
This flag is set to 1 when a stop condition is detected
after the frame is transferred.
This flag is set to 1 when no ACKnowledge is detected
from the receive device after transmission.
This flag is set to 1 when receive data is transferred from
registers SISDR to SIRDR.
In I
edge of the 9th clock cycle of the SCL signal while the
TDRE bit is 1.
In clock synchronous mode, this flag is set to 1 when the
last bit of the transmit frame is transmitted.
This flag is set to 1 when:
• Data is transferred from registers SITDR to SISDR and
• The TRS bit in the SICR1 register is set to 1 (transmit
• A start condition is generated (including retransmission)
• Slave receive mode is changed to slave transmit mode
0
at the rising edge of the SCL signal in master transmit
mode
master transmit/receive mode
bit is set to 1.
the SITDR register becomes empty.
mode)
2
2
C bus interface mode, this flag indicates that
C bus interface mode, this flag is set to 1 at the rising
(3)
STOP
b3
0
ORER_AL
b2
0
Function
21. Clock Synchronous Serial Interface
AAS
b1
0
CE_ADZ
b0
0
2
Page 467 of 725
C bus interface
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W