r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 670

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 26.7
26.5.6
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR13 bit in
the FMR1 register to 0 (lock bit enabled). The lock bit can be used to disable (lock) programming or erasing
each block. This prevents data from being written or erased inadvertently. A block status changes according to
the lock bit as follows:
• When the lock bit data is set to 0: locked (the block cannot be programmed or erased)
• When the lock bit data is set to 1: not locked (the block can be programmed and erased)
The lock bit data is set to 0 (locked) by executing the lock bit program command and to 1 (not locked) by
erasing the block. No commands can be used to set only the lock bit data to 1.
The lock bit data can be read using the read lock bit status command.
When the FMR13 bit is set to 1 (lock bit disabled), the lock bit function is disabled and all blocks are not locked
(each lock bit data remains unchanged). The lock bit function is enabled by setting the FMR13 bit to 0 (the lock
bit data is retained).
When the block erase command is executed while the FMR13 bit is 1, the target block is erased regardless of
the lock bit status. The lock bit of the erase target block is set to 1 after erasure completes.
Refer to 26.5.7 Software Commands for the details on individual commands.
The FMR13 bit is set to 0 after auto-erasure completes. This bit is also set to 0 if one of the following conditions
is met. To erase or program a different locked block, set the FMR 13 bit to 1 again and execute the block erase
or program command.
• If the FST7 bit in the FST register is changed from 0 (busy) to 1 (ready).
• If a command sequence error occurs.
• If the FMR01 bit in the FMR0 register is set to 0 (CPU mode disabled).
• If the FMSTP bit in the FM0 register is set to 1 (flash memory stops).
• If the CMDRST bit in the FMR0 register is set to 1 (erasure/writing stops).
Figure 26.7 shows the FMR13 Bit Operation Timing.
(Lock bit disable select bit)
(Ready/busy status flag)
Data Protect Function
Preliminary document
Specifications in this document are tentative and subject to change.
FMR13 Bit Operation Timing
FMR13 bit
Operation
FST7 bit
Set to 1 by a program
Erase start
Erase
Lock bit enabled
Erase completion
0 is set at the rising edge of
the FST7 bit
FST7: Bit in FST register
FMR13: Bit in FMR1 register
26. Flash Memory
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