r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 554

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 22.3
Timer RJ Set to timer mode
Timer RJ Set the pulse output level from low to start
Timer RJ Assign the TRJIO_0 pin to the corresponding port
UART0
INTx
Timer RJ Set the count source (f1, f2, f8, or fOCO)
Timer RJ Set the Synch Break width
UART0 Set to transmit/receive mode
UART0 Set the BRG count source (f1, f8, or f32)
UART0 Set the bit rate
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
Hardware LIN
Notes:
1. When the previous communication completes normally and header field transmission is
2. Although the timer-associated registers (TRJMR and TRJIOC) are set before the TRJ_0SR
(Bus collision detection, Synch Break detection, Synch Field measurement)
Bits BCIE, SBIE, and SFIE in LINCT register
(Bus collision detection, Synch Break detection, Synch Field measurement)
Bits B2CLR, B1CLR, and B0CLR in LINST register  1
performed again with the same settings, these settings can be omitted.
register is set, there is no problem with this flow for the hardware LIN.
(8-bit transfer data length, internal clock, one-stop bit, parity disabled)
U0MR register
Bits CLK0 and CLK1 in U0C0 register
U0BRG register
Setting of bits TRJIO_0SEL0 to TRJIO_0SEL2 in the TRJ_0SR register
Assign the RXD_i pin to the corresponding port
Setting of the RXD_0SEL bit in the U_0SR register
or bits RXD_1SEL0 and RXD_1SEL1 in the U_1SR register
Assign the INTx pin to the corresponding port
Setting of the INTSR0 register
Preliminary document
Specifications in this document are tentative and subject to change.
Header Field Transmission Flowchart Example (1) (i = 0 or 1, x = 1 or 2)
Bits TMOD2 to TMOD0 in TRJMR register  000b
TEDGSEL bit in TRJIOC register  1
Bits TCK0 to TCK2 in TRJMR register
TRJ register
Set the LIN operation to stop
LINE bit in LINCT register  0
Set to master mode
MST bit in LINCT register  1
Set bus collision detection to enabled
BCE bit in LINCR2 register  1
Set the LIN operation to start
LINE bit in LINCT register  1
Set interrupts to enabled
Clear the status flags
A
(1, 2)
(1, 2)
(1, 2)
(1, 2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Set the count
source and TRJ
register as
appropriate for the
Synch Break period.
Set the BRG count
source and U0BRG
register as
appropriate for the
bit rate being used.
Set the hardware LIN
function to be selected
(the TIOSEL bit in the
TRJIOC register to 1).
If the wakeup function
is not necessary, the
setting of the INTx pin
can be omitted.
In master mode, the
Synch Field
measurement-
completed interrupt
cannot be used.
22. Hardware LIN
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