r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 209
r5f21368sdfp
Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21368SDFP.pdf
(760 pages)
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Quantity
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Company:
Part Number:
r5f21368sdfp#V0
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Renesas Electronics America
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Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 13.11
Figure 13.12
13.3.8
Table 13.11
j = 0 to 23
X: 0 or 1
CPU clock
Address
CPU clock
Address
Bits b3 to b0 in
Register
DTCCR
00X0b
01X0b
10X0b
X001b
X101b
11X0b
0X11b
1X11b
The DTC requires five clock cycles to read control data allocated in the DTC control data area. The number of
clock cycles required to write back control data differs depending on the control data settings.
Figure 13.11 shows an Example of DTC Operation Timings and Figure 13.12 shows Example of DTC
Operation Timings in Chain Transfers.
Table 13.11 shows the Specifications of Control Data Write-Back Operation.
Used by CPU
Operation Timings
Read vector
Preliminary document
Specifications in this document are tentative and subject to change.
Example of DTC Operation Timings
Example of DTC Operation Timings in Chain Transfers
Specifications of Control Data Write-Back Operation
Operating
Normal
Repeat
Mode
mode
mode
Used by CPU
Read control data
Incremented
Incremented Incremented Written back Written back Written back Written back
Repeat area
Incremented
Read vector
Source
Fixed
Fixed
Fixed
Address Control
Incremented Written back Written back
Incremented Written back Written back Written back Written back
Repeat area
Destination
Read
Transfer data
Fixed
Fixed
Fixed
Read control data
Write
Write back control
Written back Written back
Written back Written back Written back
Written back Written back Written back
Written back Written back
Written back Written back Written back Written back
data
DTCCTj
Register
Control Data to be Written Back
Transfer data Write back control data
Read
Read control data
Register
DTRLDj
Write
Not written
Not written
Not written
Register
DTSARj
back
back
back
Read
Transfer data Write back control data
Write
Written back
Written back
Not written
Not written
Not written
Register
DTDARj
back
back
back
Page 178 of 725
Used by CPU
Number of
Cycles
Used by CPU
Clock
1
2
2
3
2
3
2
3
13. DTC
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