r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 558

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 22.7
Hardware LIN
Timer RJ Set pulse width measurement to start
Timer RJ Read the count status flag
Hardware LIN
Hardware LIN
Hardware LIN
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits B2CLR, B1CLR, and B0CLR in LINST register  1
Preliminary document
Specifications in this document are tentative and subject to change.
Header Field Reception Flowchart Example (2)
TSTART bit in TRJCR register  1
TCSTF bit in TRJCR register
Clear the status flags
Set Synch Break detection to start
LSTART bit in LINCT register  1
Read the RXD input status flag
RXDSF bit in LINCT register
Read the Synch Break detection flag
SBDCT bit in LINST register
RXDSF = 1?
SBDCT = 1?
TCSTF = 1?
YES
YES
YES
A
B
NO
NO
NO
Wait until timer RJ starts counting.
Zero or one cycle of the timer RJ
count source is required after timer
RJ starts counting before the TCSTF
bit is set to 1.
Wait until the RXD input to UART0
for the hardware LIN is masked.
After writing 1 to the LSTART bit, do
not apply a low level to the RXD pin
until 1 is read from the RXDSF bit.
Otherwise, the signal applied during
this time will be input directly to
UART0.
One or two cycles of the CPU clocks
and zero or one cycle of the timer RJ
count source are required until the
RXDSF bit is set to 1 after the
LSTART bit is set to 1. After this,
input to timer RJ and UART0 is
enabled.
A Synch Break for the hardware LIN
is detected.
A timer RJ interrupt can be used.
When a Synch Break is detected,
timer RJ is reloaded with the initially
set count value.
Even if the duration of the input low
level is shorter than the set period,
timer RJ is reloaded with the initially
set count value. Wait until the next
low level is input.
One or two cycles of the CPU clock
are required after Synch Break
detection before the SBDCT bit is
set to 1.
If the SBE bit in the LINCT register is
set to 0 (unmasked after Synch
Break detected), timer RJ can be
used in timer mode after the SBDCT
bit in the LINST register is set to 1
and the RXDSF bit is set to 0.
22. Hardware LIN
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