r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 143

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
10.3
Table 10.2
—: Indicates that either 0 or 1 can be set
High-speed
clock mode
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Standard operating mode is further divided into four modes.
In standard operating mode, the CPU and the peripheral function clock are supplied to operate the CPU and the
peripheral functions. Power consumption control is implemented by controlling the frequency of the system clock
or CPU clock. The higher the CPU clock frequency, the higher processing power. The lower the CPU clock
frequency, the lower the power consumption. Stopping unnecessary oscillation circuits will further reduce power
consumption.
When the clock sources for the CPU clock are switched, the new clock needs to be oscillating and stable. Allow the
new clock oscillation to stabilize in a program before switching the clocks.
Standard Operating Mode
Mode
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Preliminary document
Specifications in this document are tentative and subject to change.
Settings and Modes of Clock Associated Bits
CM4 Register
Bits CM42 to
CM40
000b
000b
000b
000b
000b
101b
101b
101b
101b
101b
001b
001b
001b
001b
001b
110b
110b
110b
110b
110b
Bits CM17 and
CM16
00b
01b
10b
11b
00b
01b
10b
11b
00b
01b
10b
11b
00b
01b
10b
11b
—
—
—
—
CM1 Register
CM14 Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
CM13 Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
CM0 Register
CM06 Bit
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
10. Power Control
Page 112 of 725
FRA0 Register
FRA00 Bit
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
0
0
0
0
0