r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 173

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 11.3
11.4.4
Address bus
CPU clock
Data bus
The following describes the interrupt sequence performed from when an interrupt request is acknowledged until
the interrupt routine is executed.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction has completed. The CPU starts the interrupt sequence from the following
cycle. However, for the SMOVB, SMOVF, SSTR, and RMPA instructions, if an interrupt request is generated
while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence.
The interrupt sequence is performed as described below.
Figure 11.3 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
(2) The FLG register is saved to a temporary register
(3) The I, D, and U flags in the FLG register are set as follows:
(4) The CPU internal temporary register
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The start address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the start address of the interrupt
routine.
Notes:
WR
RD
1. Refer to 11.8 Timer RC Interrupt, Timer RE2 Interrupt, Synchronous Serial Communication Unit
2. Temporary registers cannot be used by the user.
00000h. Then, the corresponding bit for the interrupt is set to 0 (no interrupt requested).
is entered.
The I flag is 0 (interrupt disabled)
The D flag is 0 (single-step interrupt disabled)
The U flag is set to 0 (ISP selected).
However, the U flag does not change if an INT instruction for software interrupts numbered 32 to 63 is
executed.
Interrupt Sequence
Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) for
the IR bit operations of the timer RC interrupt, timer RE2 interrupt, synchronous serial communication
unit interrupt, and flash memory interrupt.
1
Preliminary document
Specifications in this document are tentative and subject to change.
Time Required for Executing Interrupt Sequence
Address 00000h
2
information
Interrupt
3
Note:
1. The length of the undefined state depends on the instruction queue buffer.
4
A read cycle occurs when the instruction queue buffer is ready to accept instructions .
5
Undefined
Undefined
Undefined
6
7
(2)
8
is saved on the stack.
SP-2 SP-1 SP-4
9
contents
SP-2
10
(2)
contents
SP-1
in the CPU immediately before the interrupt sequence
11
contents
SP-4
12
SP-3 contents
SP-3
13
VEC
14
contents
VEC
15
VEC+1
VEC+1 contents VEC+2 contents
16
17
VEC+2
(1)
18
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11. Interrupts
19
PC
20