r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 659

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
26.3.3
Notes:
FMR11 Bit (Wait mode flash memory operation enable bit)
FMR13 Bit (Lock bit disable select bit)
After Reset
1. Do not set the FMR11 bit to 1 in stop mode, in low-power-consumption wait mode, or when low-current-
2. To set the FMR13 bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between
3. To set this bit to 0, first write 1 and then 0 immediately. Disable interrupts and DTC activation between writing 1
4. This bit is set to 0 when the FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled).
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00255h
consumption read mode is enabled.
writing 0 and writing 1.
and writing 0.
Setting the FMR11 bit to 1 allows the flash memory to operate even during wait mode. To operate the TSCU
(touch sensor) function even during wait mode, this bit must be set to 1 because the flash memory resource is
necessary for hardware operation.
When the FMR13 bit is set to 1 (lock bit disabled), the lock bit is disabled. When the FMR13 bit is set to 0, the
lock bit is enabled. Refer to 26.5.6 Data Protect Function for the details on the lock bit.
The FMR13 bit enables the lock bit function only and the lock bit data does not change. However, when a block
erase command is executed while the FMR13 bit is set to 1, the lock bit data set to 0 (locked) changes to 1 (not
locked) after erasure completes.
[Conditions for setting to 0]
The FMR13 bit is set to 0 when one of the following conditions is met.
• Completion of the program command
• Completion of the block erase command
• Generation of a command sequence error
• Transition to erase-suspend
• The FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled).
• The FMSTP bit in the FMR0 register is set to 1 (flash memory stops).
• The CMDRST bit in the FMR0 register is set to 1 (erasure/writing stops).
[Condition for setting to 1]
Set to 1 by a program.
Symbol
Symbol
FMR11
FMR13
FMR14
FMR15
FMR16
FMR17
Bit
Flash Memory Control Register 1 (FMR1)
—
—
FMR17
Preliminary document
Specifications in this document are tentative and subject to change.
b7
0
Nothing is assigned. The write value must be 0. The read value is 0.
Wait mode flash memory operation enable bit
(1)
Nothing is assigned. The write value must be 0. The read value is 0.
(2)
Data flash block A rewrite disable bit
(3, 4)
Data flash block B rewrite disable bit
(3, 4)
Data flash block C rewrite disable bit
(3, 4)
Data flash block D rewrite disable bit
(3, 4)
Lock bit disable select bit
FMR16
b6
0
FMR15
Bit Name
b5
0
FMR14
b4
0
FMR13
b3
0
0: Flash memory stops during wait mode
1: Flash memory operation enabled
0: Lock bit enabled
1: Lock bit disabled
0: Rewrite enabled (software command
1: Rewrite disabled (software command
during wait mode
acceptable)
not acceptable, no error occurred)
b2
—
0
FMR11
b1
0
Function
b0
—
0
26. Flash Memory
Page 628 of 725
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—