r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 476

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.4
20.4.1
20.4.2
20.4.1.1
20.4.1.2
20.4.2.1
20.4.2.2
The settings of the following registers can only be changed when the serial interface is disabled. Do not try to
change them while the serial interface is enabled.
The settings of the following registers can only be changed while transmission/reception is stopped. Do not try
to change them during transmission/reception.
When UART2 is not used, set the following bits to 0.
When the RTS function is used with an external clock, the RTS2 pin outputs a low level, which informs the
transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high level when a
receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting
the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is
selected.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data is output at the falling edge and receive data is
input at the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set
to 1 (transmit data is output at the rising edge and receive data is input at the falling edge of the transfer clock).
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• If the CTS function is selected, input to the CTS2 pin = Low
U2MR register: CKDIR bit
U2C0 register: Bits CLK0 and CLK1
U2MR register: Bits SMD0 to SMD2, STPS, PRY, PRYE, and IOPOL
U2BRG register: Bits b0 to b7
U2C0 register: Bits CRS, CRD, NCH, CKPOL, and UFORM
U2C1 register: Bits U2IRS, U2RRM, U2LCH, and U2ERE
U2RXDF register: DF2EN bit
U2SMR5 register: MP bit
U2SMR3 register: Bits CKPH, NODC, and DL0 to DL2
U2SMR2 register: Bits IICM2, CSC, ALS, and STAC
U2SMR register: Bits IICM, ABC, ABSCS, and SSS
U2C0 register: NCH bit
U2SMR3 register: NODC bit
Notes on Serial Interface (UART2)
Common to All Operating Modes
Clock Synchronous Serial I/O Mode
Preliminary document
Specifications in this document are tentative and subject to change.
Access to Registers
N-Channel-Open-Drain Control Bit
Transmission/Reception
Transmission
20. Serial Interface (UART2)
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