r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 462

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.17
20.3.3.8
20.3.3.9
It may happen that another device holds SCL output low and forces the clock sent from the master into a wait
state. The SCL synchronization function of UART2 automatically enters a wait state when held low by another
device, and cancels the wait state when released from low output. This function is enabled by setting the CSC
bit to 1, and disabled by setting it to 0. This function should only be used when the MCU is the master. Figure
20.17 shows the Timing of Clock Synchronization Function.
(1) SCL2 Pin Low Output Hold Function 1
Operation of clock synchronization function
Effective range of clock synchronization function
The I
byte, the slave needs to compare the receive data in the first 7 bits of the clock sent from another master
with its own address, and generate (or not generate) an acknowledge in synchronization with the 9th bit of
the clock. SCL2 pin low output hold function 1 of UART2 was created for this process.
By using this function, a low level is output to the SCL2 pin in synchronization with the SCL2 of the 9th
bit going low after the first 8 bits of data are received. This forces the master into a wait state. The function
can also generate/not generate an acknowledge after the address comparison processing by software is
completed.
This function is enabled by setting the SWC bit to 1, and disabled by setting it to 0. After the SCL2 pin has
been driven low by this function, it can be released from low level by setting the SWC bit to 0. When this
function is used to perform address comparison processing, the content of the receive buffer register is
read before the rising edge of the clock of the final bit. So take care that the read data is not changed by the
bit position. Figure 20.18 shows the Timing of SCL2 Pin Low Output Hold Function 1.
Internal baud
Internal SCL
rate clock
SCL2 pin
2
Preliminary document
Specifications in this document are tentative and subject to change.
SCL Synchronization Function
Timing of Clock Synchronization Function
SCL2 Pin Output Function
C bus sends a specified slave address in the first byte after a start condition is detected. In the first
UART2
SCL2
clock
Although the UART2 internal SCL was
originally outputting a high level, a low level
is output and the low-level count operation
starts when the SCL2 pin falls.
Transmit data is written
1
The clock synchronization function operates during this period.
2
3
4
5
Even if the UART2 internal SCL goes high, because
the SCL2 pin is low, the high-level count operation is
stopped during this period.
The UART2 internal SCL goes high, but
because the SCL2 pin is low, low is retained.
6
7
8
20. Serial Interface (UART2)
9
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