r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 538

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.31
21.4.4
Figures 21.31 to 21.34 show examples of register setting when the I
Register Setting Examples
Preliminary document
Specifications in this document are tentative and subject to change.
Register Setting Example in Master Transmit Mode (I
SICR1 register
SICR2 register
SISR register
SISR register
SICR2 register
SICR1 register
SISR register
Write transmit data to SITDR register
Write transmit data to SITDR register
Write transmit data to SITDR register
Read ACKBR bit in SIER register
Read BBSY bit in SICR2 register
Read TEND bit in SISR register
Read TDRE bit in SISR register
Read TEND bit in SISR register
Read STOP bit in SISR register
No
No
No
No
No
No
ACKBR = 0?
Initial setting
Yes
TEND = 1?
TDRE = 1?
TEND = 1?
BBSY = 0?
Last byte?
STOP = 1?
Transmit
mode?
Start
End
TRS bit  1
MST bit  1
SCP bit  0
BBSY bit  1
TEND bit  0
STOP bit  0
SCP bit  0
BBSY bit  0
TRS bit  0
MST bit  0
TDRE bit  0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Master receive mode
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
• Set the STOP bit in the SISR register to 0.
• Set the IICSEL bit in the IICCR register to 1.
• Set the MSTIIC bit in the MSTCR1 register to 0.
(1) Determine the state of the SCL and SDA lines.
(2) Set to master transmit mode.
(3) Generate a start condition.
(4) Set the transmit data of the 1st byte (slave address + R/W).
(5) Wait until 1 byte of data is transmitted.
(6) Determine the ACKBR bit from the specified slave device.
(7) Set the transmit data after 2nd byte (except the last byte).
(8) Wait until the SITDR register is empty.
(9) Set the transmit data of the last byte.
(10) Wait for end of transmission of the last byte.
(11) Set the TEND bit to 0.
(12) Set the STOP bit to 0.
(13) Generate a stop condition.
(14) Wait until a stop condition is generated.
(15) Set to slave receive mode.
Set the TDRE bit to 0.
2
C bus interface is used.
21. Clock Synchronous Serial Interface
2
C bus Interface Mode)
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