r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 12
r5f21368sdfp
Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21368SDFP.pdf
(760 pages)
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Part Number:
r5f21368sdfp#V0
Manufacturer:
Renesas Electronics America
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10 000
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12.
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12.1
12.2
12.3
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
11.2.10 INT Interrupt Input Pin Select Register 0 (INTSR0) .............................................................................. 137
11.3.1
11.3.2
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
11.4.8
11.4.9
11.4.10 Interrupt Priority Level Selection Circuit ................................................................................................ 147
11.5.1
11.5.2
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
12.2.1
Event Link Controller (ELC) .............................................................................................................. 156
Registers ....................................................................................................................................................... 130
Interrupts and Interrupt Vectors ................................................................................................................... 138
Interrupt Control ........................................................................................................................................... 141
INT Interrupt ................................................................................................................................................ 148
Key Input Interrupt ....................................................................................................................................... 150
Address Match Interrupt .............................................................................................................................. 151
Timer RC Interrupt, Timer RE2 Interrupt, Synchronous Serial Communication Unit Interrupt, and Flash
Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) .................................................... 152
Notes on Interrupts ....................................................................................................................................... 153
Overview ...................................................................................................................................................... 156
Registers ....................................................................................................................................................... 157
Operation ...................................................................................................................................................... 159
Interrupt Control Register
(FMRDYIC, INT4IC, TRCIC_0, TRE2IC, U2TIC, U2RIC, KUPIC, ADIC, SSUIC_0/IICIC_0,
U0TIC_0, U0RIC_0, U0TIC_1, U0RIC_1, INT2IC, TRJIC_0, TRB2IC_0, INT1IC, INT3IC, INT0IC,
U2BCNIC, VCMP1IC, VCMP2IC, TSCUIC) ........................................................................................ 131
External Input Enable Register 0 (INTEN) ............................................................................................. 132
External Input Enable Register 1 (INTEN1) ........................................................................................... 133
INT Input Filter Select Register 0 (INTF) ............................................................................................... 134
INT Input Filter Select Register 1 (INTF1) ............................................................................................. 134
INT Input Polarity Switch Register (INTPOL) ....................................................................................... 135
Key Input Interrupt Enable Register (KIEN) .......................................................................................... 135
Address Match Interrupt Address ij Register (AIADRij) (i = 0 or 1, j = L or H) ................................... 136
Address Match Interrupt Enable i Register (AIENi) (i = 0 or 1) ............................................................. 136
Fixed Vector Table ................................................................................................................................... 138
Relocatable Vector Table ......................................................................................................................... 139
I Flag ........................................................................................................................................................ 141
IR Bit ....................................................................................................................................................... 141
Bits ILVL2 to ILVL0, IPL ....................................................................................................................... 141
Interrupt Sequence ................................................................................................................................... 142
Interrupt Response Time .......................................................................................................................... 143
IPL Change when Interrupt Request is Acknowledged ........................................................................... 143
Saving Registers ...................................................................................................................................... 144
Returning from Interrupt Routine ............................................................................................................ 146
Interrupt Priority ...................................................................................................................................... 146
INTi Interrupt (i = 0 to 4) ........................................................................................................................ 148
INTi Input Filter (i = 0 to 4) .................................................................................................................... 149
Reading Address 00000h ......................................................................................................................... 153
SP Setting ................................................................................................................................................ 153
External Interrupt, Key Input Interrupt .................................................................................................... 153
Changing Interrupt Sources ..................................................................................................................... 154
Rewriting Interrupt Control Register ....................................................................................................... 155
Event Output Destination Select Register n (ELSELRn) (n = 0 to 4, 8, 9, 11 to 16) .............................. 157
A - 5
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