r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 203

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 13.3
Figure 13.4
Write 0 to the interrupt source
flag in the status register
Write back control data
Write back control data
DTC activation source
DTC activation source
Read control data
Read control data
Read DTC vector
Read DTC vector
Transfer data
Transfer data
CHNE = 1?
CHNE = 1?
generation
NMIF = 1?
generation
NMIF = 1?
Branch 1
Branch 1
End
End
Preliminary document
Specifications in this document are tentative and subject to change.
DTC Internal Operation Flowchart (i = 0 to 3, 5, or 6) (j = 0 to 23) when DTC Activation
Source is not Timer RC, Timer RE2, SSU/I
Source
DTC Internal Operation Flowchart (i = 0 to 3, 5, or 6) (j = 0 to 23) when DTC Activation
Source is Timer RC, Timer RE2, or TSCU Interrupt Source
No
No
No
No
Yes
Yes
Yes
Yes
Write back control data
Write back control data
Read control data
Read control data
Transfer data
Transfer data
CHNE = 1?
CHNE = 1?
No
No
Yes
Yes
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
DTCENi0 to DTCENi7: Bits in DTCENi registers
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
DTCENi0 to DTCENi7: Bits in DTCENi registers
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
repeat mode
repeat mode
Generate an interrupt request
Generate an interrupt request
Write 0 to the bit among
Write 0 to the bit among
Write back control data
Write back control data
DTCENi0 to DTCENi7
DTCENi0 to DTCENi7
Interrupt handling
Interrupt handling
Transfer data
Transfer data
for the CPU
for the CPU
CHNE = 1?
CHNE = 1?
2
C bus, Flash Memory, or TSCU Interrupt
No
No
Yes
Yes
Write back control data
Write back control data
Read control data
Read control data
Transfer data
Transfer data
CHNE = 1?
CHNE = 1?
No
No
Page 172 of 725
Yes
Yes
13. DTC