r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 364

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
18.2.10 Timer RE2 Control Register (TRECR) in Real-Time Clock Mode
Notes:
TRECR register
RTCRST bit in
AADJE Bit (Timer RE2 automatic correction function enable bit)
TREOE Bit (Timer RE2 output enable bit)
LFLAG Bit (Leap year flag)
1. When the RTCRST bit is set to 1, the TREYR register is set to 00b. As year 2000 is a leap year, the initial value
2. Set the RTCRST bit to 0 after setting it to 1.
After reset by
Bit
b0
b1
b2
b3
b4
b5
b6
b7
After Reset
of the LFLAG bit is set to 1.
Change this bit when the BSY bit in the TRESEC register is 0 (data not being updated) and the TADJSF bit in
the TREIFR register is 0 (no correction).
Change this bit when the RUN bit is set to 0 (count stops).
The LFLAG bit is set to 1 (leap year) when the value of the TREYR register is 00 or a multiple of four. When
the LFLAG bit is set to 1, the number of days in February becomes 29.
Read this bit when the BSY bit is 0 (data not being updated).
Address 00177h
Symbol
RTCRST Timer RE2 reset bit
Symbol
TREOE Timer RE2 output enable bit
AADJE
LFLAG
CCLR
HR24
RUN
PM
Bit
Preliminary document
Specifications in this document are tentative and subject to change.
RUN
Timer RE2 automatic correction
function enable bit
Leap year flag
(1)
Set to 0.
(2)
a.m./p.m. bit
Operating mode select bit
Timer RE2 operation start bit
b7
0
0
HR24
b6
0
0
Bit Name
PM
b5
0
0
RTCRST
b4
0
X
0: Automatic correction function disabled
1: Automatic correction function enabled
0: TMRE2O output disabled
1: TMRE2O output enabled
0: Ordinary year
1: Leap year
When this bit is set to 1, the registers and bits
listed in Table 18.5 are initialized and the counter
control circuit is initialized.
0: a.m.
1: p.m.
0: 12-hour mode
1: 24-hour mode
0: Count stops
1: Count starts
(correction by software enabled)
(correction by software disabled)
CCLR
b3
X
0
LFLAG
b2
1
1
Function
TREOE
b1
X
0
AADJE
b0
0
0
Page 333 of 725
18. Timer RE2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R