r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 656

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
26.3.2
Notes:
FMR01 Bit (CPU rewrite mode select bit)
FMR02 Bit (EW1 mode select bit)
FMSTP Bit (Flash memory stop bit)
After Reset
1. To set this bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between writing 0
2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is
3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the
4. To set the FMR01 bit to 0 (CPU rewrite mode disabled), set it when the RDYSTI bit in the FST register is 0 (no
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00254h
and writing 1.
set to 1 (CPU rewrite mode enabled). Do not set FMSTP bit to 1 (flash memory stops) when the FMR01 bit is 0
(CPU rewrite mode disabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in the
FST register is 1 (ready).
FST register is set to 0 (busy).
flash ready status interrupt requested) and the BSYAEI bit is 0 (no flash access error interrupt requested).
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software
commands.
When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected.
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Write to the FMSTP bit by a program transferred to the RAM.
To reduce the power consumption further in high-speed on-chip oscillator mode, low-speed on-chip oscillator
mode (XIN clock stopped), and low-speed clock mode (XIN clock stopped), set the FMSTP bit to 1. Refer to
10.6.10 Stopping Flash Memory for details.
Symbol RDYSTIE BSYAEIE CMDERIE CMDRST FMSTP
CMDERIE Erase/write error interrupt enable bit
CMDRST Erase/write sequence reset bit
RDYSTIE Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled
BSYAEIE
Bit
FMSTP
Symbol
FMR01
FMR02
Flash Memory Control Register 0 (FMR0)
—
Preliminary document
Specifications in this document are tentative and subject to change.
b7
0
Reserved
CPU rewrite mode select bit
(1, 4)
EW1 mode select bit
(1)
Flash memory stop bit
(2)
(3)
Flash access error interrupt enable bit 0: Flash access error interrupt disabled
b6
0
Bit Name
b5
0
b4
0
Set to 0.
0: CPU rewrite mode disabled
1: CPU rewrite mode enabled
0: EW0 mode
1: EW1 mode
0: Flash memory operates
1: Flash memory stops
When the CMDRST bit is set to 1, the
erase/write sequence is reset and
erasure/writing can be forcibly stopped.
The read value is 0.
0: Erase/write error interrupt disabled
1: Erase/write error interrupt enabled
1: Flash access error interrupt enabled
1: Flash ready status interrupt enabled
b3
0
(Low-power consumption state, flash memory
initialization)
FMR02
b2
0
Function
FMR01
b1
0
b0
—
0
26. Flash Memory
Page 625 of 725
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W