r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 542

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.35
Figure 21.36
21.4.5
21.4.6
f1 sampling clock
SCL or SDA
input signal
The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure
21.35 shows the Noise Canceller Block Diagram.
The noise canceller consists of two cascaded latch and match detection circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
When the I
states:
• The SCL signal is held low by a slave device.
• The rising speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
In the bit synchronization circuit, the SCL input is monitored after a specified time (MT) from the rising of the
SCL output to check whether SCL has become high level. If the SCL is pulled low level by a slave or the rising
speed is reduced by a load on the SCL line, it is recognized that SCL is not pulled high level, and the timing for
falling of SCL is delayed.
Figure 21.36 shows the Timing of Bit Synchronization Circuit, and Table 21.12 lists the Time between
Changing SCL Signal from Low Output to High Impedance and Monitoring SCL Signal.
Noise Canceller
Bit Synchronization Circuit
Preliminary document
Specifications in this document are tentative and subject to change.
Noise Canceller Block Diagram
Timing of Bit Synchronization Circuit
2
C bus interface is set to master mode, the high period may become shorter in the following two
SCL monitor timing
Reference clock of
Internal SCL
SCL
MT
SCL
21. Clock Synchronous Serial Interface
MT
0
1
Page 511 of 725
Internal SCL
or SDA signal