r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 399

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
18.5
Table 18.7
Real-time clock
period/overflow
Alarm/compare match Real-time clock
The interrupt sources for timer RE2 are listed below:
• Periodic interrupts (0.25 seconds, 0.5 seconds, 1 second, minutes, hours, a day, a month, a year)
• Alarm interrupt
• Compare match interrupt
• Overflow interrupt
Table 18.7 lists Timer RE2 Interrupt Sources.
When an interrupt is used, set the registers other than the TRECR register while the RUN bit in the TRECR register
is 0 (count stops), and set the RUN bit to 1 (count starts).
[Real-time clock mode]
When an enabled periodic interrupt source is generated, the RTCF bit in the TREIFR register is set to 1 (interrupt
requested), and an interrupt request is generated.
When the alarm time and the counter match, the ALIF bit in the TREIFR register is set to 1 (interrupt requested).
When an alarm interrupt is enabled, an interrupt request is generated.
[Compare match timer mode]
When the compare match timer overflows, the OVIF bit in the TREIFR register is set to 1 (interrupt requested).
When the OVIE bit in the TRIER register is 1 (overflow interrupt enabled), an interrupt request is generated.
When the compare match timer is compared and matches, the CMIF bit in the TREIFR register is set to 1 (interrupt
requested). When the CMIE bit in the TREIER register is 1 (compare match interrupt enabled), an interrupt request
is generated.
Source
Interrupt Sources
Preliminary document
Specifications in this document are tentative and subject to change.
Timer RE2 Interrupt Sources
Operating mode
Real-time clock
mode
Compare match
timer mode
mode
Compare match
timer mode
Periodic interrupt
triggered every 0.25
seconds
Periodic interrupt
triggered every 0.5
seconds
Periodic interrupt
triggered every
second
Periodic interrupt
triggered every minute
Periodic interrupt
triggered every hour
Periodic interrupt
triggered every day
Periodic interrupt
triggered every month
Periodic interrupt
triggered every year
Overflow interrupt
Alarm interrupt
Compare match
interrupt
Source Name
0.25-second period
0.5-second period
The TRESEC register is
updated (one-second
period).
The TREMIN register is
updated (one-minute period).
The TREHR register is
updated (one-hour period).
The TREDY register is
updated (one-day period).
The TREMON register is
updated (one-month period).
The TREYR register is
updated (one-year period).
When the compare match
timer overflows.
When the alarm time set by
the alarm register (TREAMN,
TREAHR, or TREAWK
register only with enable bit
set as 1) and the counter
match.
When the compare match
timer is compared and
matches.
Interrupt Source
SEIE025
SEIE05
SEIE
MNIE
HRIE
DYIE
MOIE
YRIE
OVIE
ALIE
CMIE
Interrupt Enable Bit
Page 368 of 725
18. Timer RE2