r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 539

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.32
Notes:
1. Do not generate interrupts during process steps (1) to (3).
2. For 1 byte of data reception, skip steps (2) to (6) after step (1) and jump to process step (7). Process step (8) is a dummy
read from the SIRDR register.
SISR register
SICR1 register
SISR register
SIER register
SIER register
SICR1 register
SISR register
SICR2 register
SICR1 register
SICR1 register
Preliminary document
Specifications in this document are tentative and subject to change.
Register Setting Example in Master Receive Mode (I
Read RDRF bit in SISR register
Read RDRF bit in SISR register
Read STOP bit in SISR register
Dummy read SIRDR register
No
No
No
Master receive mode
Read SIRDR register
Read SIRDR register
Read SIRDR register
Last receive - 1?
Yes
Yes
Yes
RDRF = 1?
RDRF = 1?
STOP = 1?
End
TEND bit  0
TRS bit  0
TDRE bit  0
CEIE_ACKBT bit  0
CEIE_ACKBT bit  1
RCVD bit  1
STOP bit  0
SCP bit  0
BBSY bit  0
RCVD bit  0
MST bit  0
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1) Set the TEND bit to 0 and set to master receive mode.
(2) Set the CEIE_ACKBT bit to the transmit device.
(3) Dummy read the SIRDR register.
(4) Wait until 1 byte is received.
(5) Determine (last receive - 1).
(6) Read the receive data.
(7) Set the ACKBT bit of the last byte and set continuous
(8) Read the receive data of (last byte - 1).
(9) Wait until the last byte is received.
(10) Set the STOP bit to 0.
(11) Generate a stop condition.
(12) Wait until a stop condition is generated.
(13) Read the receive data of the last byte.
(14) Set the RCVD bit to 0.
(15) Set to slave receive mode.
Set the TDRE bit to 0.
receive operation to disable (RCVD = 1).
21. Clock Synchronous Serial Interface
2
C bus Interface Mode)
(1, 2)
(1)
(2)
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