r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 537

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.30
21.4.3.3
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the SICR1 register is 1 and input when the MST bit is 0.
Figure 21.30 shows the Operation Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows:
(1) Set the ICE bit in the SICR1 register to 1 (transfer operation enabled). Then, set bits CKS0 to CKS3 in the
(2) Set the MST bit to 1 while the transfer clock is being output. This will start the output of the receive clock.
(3) When the receive operation is completed, data is transferred from registers SISDR to SIRDR and the
(4) When the MST bit is 1, set the RCVD bit in the SICR1 register to 1 (next receive operation disabled) to
SIRDR register
SISDR register
SICR1 register
SICR1 register
SISR register
SICR1 register and the MST bit (initial setting).
RDRF bit in the SISR register is set to 1. When the MST bit is set to 1, the clock is output continuously
since the next byte of data is enabled for reception. Continuous reception is enabled by reading the SIRDR
register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is 1, an overrun
is detected and the ORER_AL bit in the SISR register is set to 1. At this time, the last receive data is
retained in the SIRDR register.
stop reception before reading the SIRDR register. The SCL signal is held high after the following byte of
data reception is completed.
RDRF bit in
processing
MST bit in
TRS bit in
Program
(input)
SDA
SCL
Preliminary document
Specifications in this document are tentative and subject to change.
Receive Operation
Operation Timing in Receive Mode (Clock Synchronous Serial Mode)
0
(2) Set MST bit to 1
(when transfer clock is output).
b0
1
b1
Data 1
2
b6
7
(3) Read SIRDR register.
b7
8
b0
Data 1
1
21. Clock Synchronous Serial Interface
Data 2
b6
7
8
b7
(3) Read SIRDR register.
Data 2
1
b0
Data 3
2
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