r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 524

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r5f21368sdfp

Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r5f21368sdfp#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.18
21.4.2
(1) I
(2) I
Legend:
S
SLA : Slave address
R/W : Indicates the direction of data transmission/reception. Data is transmitted when:
A
DATA : Transmit/receive data
P
21.4.2.1
21.4.2.2
(b) I
(a) I
2
2
C bus format
C bus timing
When the MS bit in the SIMR2 register is set to 0, I
Figure 21.18 shows the I
of 8 bits.
: Start condition
: Acknowledge
: Stop condition
In the I
this module operates as a slave device, slave addresses can be programmed using bits SVA0 to SVA6 in the
SIMR2 register. However, this does not apply to the “general call address” and the “start byte” defined in the
I
• General call address (0000_000_0)
• Start byte (0000_000_1)
2
The master device changes the SDA signal from high to low while the SCL signal is held high.
R/W value is 1: From the slave device to the master device
R/W value is 0: From the master device to the slave device
The receive device sets the SDA signal to low.
The master device changes the SDA signal from low to high while the SCL signal is held high.
2
2
C bus format (When start condition is retransmitted, MS = 0)
Since all the devices are addressed, an acknowledge signal is returned.
All the devices cannot return any acknowledge signal.
C bus format (MS = 0)
C bus specification.
SDA
SCL
S
S
1
1
I
2
2
C bus format, the first 1 byte immediately after a start condition is specified as a slave address. When
C bus Interface Mode
S
Preliminary document
Specifications in this document are tentative and subject to change.
I
I
I
2
2
2
C bus Format and Bus Timing
C bus Format
C bus Slave Addressing
SLA
SLA
7
7
1 to 7
SLA
1
1
R/W
R/W
8
1
1
R/W
2
C bus Format and Bus Timing. The first frame following the start condition consists
A
A
1
1
9
A
DATA
DATA
n
n1
1 to 7
m1
DATA
8
A
1
m
A/A
1
2
9
C bus interface mode is used for communication.
A
S
1
A/A
1
1 to 7
SLA
7
P
1
DATA
1
8
Number of transfer bits (n = 1 to 8)
Number of transfer frames (m = 1 or more)
21. Clock Synchronous Serial Interface
R/W
Upper: Number of transfer bits (n1, n2 = 1 to 8)
Lower: Number of transfer frames (m1, m2 = 1 or more)
1
9
A
A
1
P
DATA
n2
m2
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A/A
1
P
1

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